Integrated circuit chips are fabricated by forming an array of chips on silicon wafers and dicing the wafer to produce individual chips. The individual chips are then attached to chip carriers, ceramic or organic modules or circuit boards using various techniques, the most common methods include reflow solder or wire bonding. The reflow solder technique uses the reflow of Pb/Sn solder bumps (also known as C4 or controlled collapse chips connect) formed on the chip pads at wafer level to attach the chip. The other technique known as wire bonding or tape automated bonding (TAB) may be done by etching bumps on the leads or applying bumps (typically Al) to the chips. It is understood in the industry that when reference is made to bumped chips. It usually refers to Pb/Sn solder bumps, or TAB bumped chips. The bumped chips may be mounted to carriers either individually (single chip modules) or in groups (multi-chip modules).
Certain reliability testing of semiconductor chips, known as burn-in testing and the like, requires prolonged power-up of the chip, often at elevated temperatures and voltages. While the chips may be easily functionally tested while in wafer form, this type of testing is difficult to do at wafer level due to problems associated with power distribution, wiring, and test channel density. These problems become even more difficult as I/O counts increase. Consequently burn-in testing has been traditionally done after the chips have been mounted and connected to the next level of packaging. A problem with this approach, however, is the cost of packaging chips that will fail such testing when attachments and wiring techniques are used that cannot be easily reworked. In this instance, reworks means removing a failing chip from the package and replacing it with another good chip. Subsequently the new chip must be burned in, forcing the other chips to undergo unnecessary additional stress. Therefore there is great advantage to be gained by individual chip (also known as bare die) testing.
Turning to the prior art, a socket for testing individual Pb/Sn solder bumped chips is described in U.S. Pat. No. 5,073,117 to Satwinder et. al., employing a plurality of cantilever beams extending from the periphery of the socket to contact individual solder bumps. However this approach is limited to testing chips having one or at most two or three rows of peripheral bumps and cannot be used with chips having an array of solder bumps extending into the interior portion of the chip surface.
U.S. Pat. No. 5,206,585 to Chang et. Al, describes a method of contacting an array of Pb/Sn solder bumps using a layer of anisotropic conductive material. The conductive column within the material forms a connection between individual bumps. The columns of conductors are described to be on 200 micron pitches. This is sufficient find for 100 micron bumps on 200 micron pitches, but is not fine enough when the bump size decreases 25 micron bumps on 50 micron pitches, which are commonly used. Also, only bumped chips can be tested by this method. Because the contacting method of this invention is non-penetrating of the bump, oxide formations on the bump and the attending contact resistance problem are concerns.
U.S. Pat. Nos. 5,523,696 and 5,528,159 both to Charlton et. al., describe a socket that can contact an array of Pb/Sn solder bumps using vertical dendritic growths or coated polymeric cones. This resolves the oxide problem by penetrating to the bulk material. A particular disadvantage of invention lies in the formation of the contacting structures produced. They are not regular in shape or pattern within an individual contact pad or from a contact pad to contact pads thus leading to a non-uniformity of contact pressure across all bumps of the array. This non-uniformity of pressure can increase the difference in contact resistance from bump to bump, affecting the testing as well as deform each bump differently, leading to attach problems when the chip is reflow attached to the carrier due to variations in flux inclusion within the bump.
It is well known in the art to temporally attach Pb/Sn solder bumped chips to a test substrate, perform the test, remove the chip by re-melting the bumps, and then reform the bumps. However, this technique, besides being expensive and potentially degrading the quality of the bump, does not work for chips designed to be wire or tab bonded. U.S. Pat. No. 5,374,893 to Koopman et. al., describes a similar technique by forming a sacrificial layer on a temporary substrate to reflow Pb/Sn solder bumps to attach to the chip. After testing, the sacrificial layer is dissolved into the C4. Using this approach, the temporary substrate must then be reworked after each use.
Still another concern of individual chip level testing is the difference in lateral coefficients of expansion between the chip and test socket or interposer used within the socket. This difference can deform the soft Pb/Sn bumps leading to chip attach problems during reflow or produce very large deformations in chip pad surfaces making wire or tab bonding unreliable. U.S. Pat. No. 5,457,344 to Bartelink describes a contacting fixture that compensates the differences due to thermal expansion. The connector however is relatively complicated, fragile and expensive to fabricate.
Therefore, there is a need in the industry for a method of contacting both bumped and non-bumped individual chips reliably and with minimum impact to the chip.